Modem integrated circuits often employ charge-pump circuitry in order to provide an internal supply voltage greater than that of the externally available power source. Such circuits are typically employed in lightweight, low-power products where power (e.g., battery power) and space are at a premium.
In general, charge pumps employ a combination of diode elements, capacitor elements, and switching elements to provide a substantially stable output voltage that is greater than the supply voltage (V.sub.DD). In the most basic implementation of a charge pump, a capacitor is charged to a predetermined voltage during a first phase, then placed in series with a switched supply voltage during the second phase such that a portion of the combined charge is transferred through a diode element to a reservoir capacitor and/or a subsequent charge pump stages. As shown in FIG. 1, for example, a first stage 120 includes a capacitor 108 initially charged to V.sub.DD. Upon application of the CK signal 112 during the first phase, the voltage at node 105 is increased. A portion of the charge at node 105 is then transferred to node 107 in the second stage 122 through the switching action of clock 112 and complementary clock 114. Thus, the capacitor charge is effectively "pumped" toward the output 107, through diodes 104 and 106, by the switching action of clocks 112 and 114. Output node 107 (which is typically attached to a load having a known input capacitance and resistance) thereby achieves a steady state voltage that is higher than V.sub.DD by about a factor of two (i.e., the actual output voltage is 2V.sub.DD -2V.sub.d, where V.sub.d is the diode threshold voltage, typically about 0.7V). Those skilled in the art will appreciate that additional stages may be used to further increase the output.
The charge pump capacitors may be implemented using a variety of technologies. For example, a metal-oxide-semiconductor field-effect-transistor (MOSFET) may be employed as a capacitive element by tying its, drain, source, and substrate terminals together and using the resultant structure as a two-terminal device. Illustrative cross-sectional and schematic diagrams of n-channel and p-channel MOS capacitors are shown in FIGS. 2A and 2B respectively. Due to their relatively high capacitance per unit area, MOS capacitors are desirable in cases where high-efficiency passive capacitors are not available.
Under static biasing conditions, the MOS capacitor can be characterized by three distinct biasing regions: accumulation, depletion, and inversion. The accumulation region corresponds to the case where the majority carrier concentration is greater near the oxide-semiconductor interface than in the bulk of the semiconductor. Ideally, for an n-channel MOS capacitor (referred to herein as an "nFET capacitor"), accumulation occurs when the gate voltage is less than zero. Depletion refers to the case where the carrier concentration at the oxide-semiconductor interface is less than that of the bulk semiconductor. In an nFET capacitor, this occurs when the gate voltage is greater than zero. Inversion occurs when the gate voltage is greater than or equal to the effective threshold voltage (V.sub.th) of the structure, which depends on a number of factors, for example, channel dimensions and doping concentrations. The same biasing regions, using reversed polarities, also apply to p-channel MOS capacitors (referred to herein as "pFET capacitors").
The efficiency of a MOS capacitor is a strong function of biasing region. That is, the value of capacitance depends upon whether the MOS capacitor is operating in the accumulation, depletion, or inversion region. This dependence is clear in FIG. 3, which shows a qualitative voltage-capacitance relationship for a typical nFET capacitor. The capacitance value achieves a maximum value close to C.sub.max in accumulation region 302 and toward higher V.sub.G levels within inversion region 306. The capacitance value varies greatly within depletion region 304, and reaches a minimum at a point close to the onset of inversion (at approximately V.sub.G =V.sub.th =0.7 V). This minimum capacitance is approximately one fourth of C.sub.max. Additional background information regarding the capacitance-voltage characteristics of MOS structures can be found in a number of references, for example: Pierret, Modular Series on Solid State Devices, Vol. IV: Field Effect Devices (1983).
Known methods for using MOS capacitors in connection with charge pump circuitry exclusively involve using nFET capacitors operating in the inversion mode. The power supply voltage has traditionally been much higher than the threshold voltage of the FETs. As the voltage drop across the FET capacitor is usually higher than (V.sub.DD -V.sub.d)/2, the operation in deep inversion region is always guaranteed. Thus, this scheme is suitable for charge pumps whose internal supply voltage is substantially greater than Vth, and where the nFET capacitor remains relatively close to Cmax (i.e., operating in region 308 of FIG. 3). In recent years, however, in accordance with the trend toward miniaturization and power conservation in modern electronics, the internal supply voltage available to the charge pump has been reduced to the point that nFET capacitors have become less and less efficient. More particularly, the nFET has been forced to operate in a region closer to Vth, where its capacitance value is lower and can vary significantly during operation. Moreover, the FET threshold voltage cannot keep up with this trend because lower V.sub.th means higher leakage current, and higher leakage current results in higher power dissipation, thereby defeating the purpose of lowering V.sub.DD.
Similarly, known systems also exhibit unsatisfactory area efficiency. Area efficiency refers to the overall area of the charge pump as compared to its ability to deliver a certain current at the generated voltage.
Moreover, the use of nFET capacitors is unsatisfactory in that the capacitance value in the inversion region is inversely related to switching frequency. That is, as charge pump clock speeds increase, the inversion portion (306) of FIG. 3 flattens out to a capacitance value much less than Cmax.
Systems are therefore needed to overcome these and other limitations of the prior art.